Capping layer for a semiconductor device and a method of fabrication

ABSTRACT

Numerous embodiments of a method and apparatus for a capping layer are disclosed. In one embodiment, a method of forming a capping layer for a semiconductor device comprises forming one or more layers on at least a portion of the top surface of a semiconductor device, substantially planarizing at least one of the one or more layers, annealing at least a portion of the semiconductor device, and removing a substantial portion of the one or more layers, using one or more etching processes.

This is a Divisional application of Ser. No.: 10/319,734 filed Dec. 12,2002, which is presently pending.

BACKGROUND

As part of the fabrication process for semiconductor devices such asintegrated circuits (ICs), devices residing on a wafer typically undergoa heat treating or thermal annealing process, which may follow formationof one or more gate structures and implantation or doping of the wafer,for example. Annealing may serve several purposes, including physicalrepair of the silicon lattice structure following doping, and activationof the dopant.

Laser annealing is one particular annealing process that may be utilizedin the fabrication of semiconductor devices, and may provide rapidannealing of selected portions of a semiconductor device. Laserannealing may be performed using many different techniques, includingpulsed and stepped laser annealing. Laser annealing provides heating ofselected portions of a silicon wafer, rather than heating of the entirewafer to a uniform temperature as in alternative annealing methods.

Present state of the art annealing methods such as laser annealing mayresult in uneven heating or temperature non-uniformity of surfaces of asemiconductor device, due at least in part to varying topographies ortopologies of a device that are created during the fabrication process,and the nature of laser light being somewhat pattern dependent. Forexample, the topography of a semiconductor device may vary across thesurface of the device. A surface on top of a substrate, in an areabetween two gates, may be in a lower relative vertical position than atop surface of a gate, for example. Because the topography differs amongthese surface points, a laser used in an annealing process may beabsorbed or reflected differently depending on the pattern of thesurface being irradiated. This may result in uneven heating among thesesurface points, which may result, for example, in the production ofundesirable physical characteristics in a semiconductor device. A needexists, therefore, of a method and apparatus of reducing these thermaleffects.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter regarded as embodiments of the claimed subject matteris particularly pointed out and distinctly claimed in the concludingportion of the specification. Embodiments of the claimed subject matter,however, both as to organization and method of operation, together withobjects, features, and advantages thereof, may best be understood byreference to the following detailed description when read with theaccompanying drawings in which:

FIG. 1 a is an illustration of a silicon substrate with devices formedthereon;

FIG. 1 b is a illustration of a silicon substrate with devices formedthereon, wherein one or more devices has a layer formed thereon;

FIG. 2 a is a illustration of a silicon substrate with devices formedthereon, wherein one or more devices has a first layer formed thereon;and

FIG. 2 b is a illustration of a silicon substrate with devices formedthereon, wherein one or more devices have a first layer and a secondlayer formed thereon.

DETAILED DESCRIPTION

Embodiments of the claimed subject matter may comprise a capping layerfor a semiconductor device and a method of fabrication. As mentionedpreviously, during fabrication of a device such as a semiconductordevice, one or more fabrication processes may result in the productionof a partially fabricated device with varying topologies and/ortopographies. This may result in uneven heating of one or more areas ofthe device when undergoing heating processes such as laser annealing,due at least in part to these variations, and the tendency of laserlight to be pattern dependent. More specifically, laser light tends tobe coherent, meaning, for example, that the reflectivity of laser lightmay vary as light is exposed to devices of various patterns. Inoperation, and in the context of topography variation, surface points ona device that form a particular topography relative to other surfacepoints on the device may be over-heated, due at least in part on thelaser being absorbed more or reflected less than other areas.Overheating may result in the altering the material properties of adevice and eventual formation of salicide, and/or softening of surfacematerials and/or sub-surface materials. Softening may lead todeformation of the semiconductor device surface, and may prevent orreduce the capacity to form abrupt junctions on the semiconductordevice, as just an example.

Just as topography differs among surface points, topology may alsodiffer among surface points. In this regard, a device substrate mayinclude sections having different optical, chemical and/or electricalproperties. For example, a substrate may include a substrate section, asource/drain region, and a gate oxide area, for example. Surface pointson top of these materials may have a similar topography, but thetopology differs, which affects how the surface points react to heat.Specifically, those surface points in respect of which the surfacematerials and/or sub-surface materials have relatively lower meltingpoints may be over-heated, in comparison to surface points having arelatively higher melting point. Differences in the thermal conductivityof various materials can also result in an uneven heating of thesurfaces, due at least in part to the different amounts of energyabsorbed in different regions of the device. In this context, asemiconductor device may alternatively be referred to as a transistor oran integrated circuit (IC).

Embodiments of the claimed subject matter may comprise a capping layerfor a semiconductor device, and a method of fabrication. The method maycomprise forming a capping layer comprising a first and second layer,wherein the first layer is formed on at least a portion of the topsurface of a semiconductor device, a second layer is formed on at leasta portion of the first layer, and the second layer is substantiallyplanarized prior to annealing at least a portion of the device.

It is worthy to note that any reference in the specification to “oneembodiment” or “an embodiment” means that a particular feature,structure, or characteristic described in connection with the embodimentis included in at least one embodiment of the claimed subject matter.The appearances of the phrase “in one embodiment” in various places inthe specification are not necessarily all referring to the sameembodiment.

Numerous specific details may be set forth herein to provide a thoroughunderstanding of the embodiments of the claimed subject matter. It willbe understood by those skilled in the art, however, that the embodimentsof the claimed subject matter may be practiced without these specificdetails. In other instances, well-known methods, procedures andcomponents have not been described in detail so as not to obscure theembodiments of the claimed subject matter. It can be appreciated thatthe specific structural and functional details disclosed herein may berepresentative and do not necessarily limit the scope of the claimedsubject matter.

Referring now in detail to the drawings wherein like parts aredesignated by like reference numerals throughout, there is illustratedin FIG. 1 a a semiconductor device that may be configured to incorporateat least one embodiment of the claimed subject matter, and may comprise,for example, a partially formed metal oxide semiconductor (MOS) basedtransistor. Shown in FIG. 1 a is a partially formed transistor for anintegrated circuit. As is well-known, integrated circuits are usuallymanufactured on silicon or other semiconductor substrates. An integratedcircuit may be comprised of millions of transistors such as partiallyformed transistor 100 of FIG. 1 a. Devices such as partially formedtransistor 100 typically include a substrate 108, which may comprisesilicon, for example. A gate dielectric 106 is typically formed on thesubstrate, and may comprise silicon dioxide or other dielectricmaterial, for example. Gate 102 is typically formed on the gatedielectric. Gate 102 is formed from an electrically conductive material,such as a metal or polysilicon based material, for example. Spacers 110may be formed on the sides of the gate 102 and gate dielectric 106, andmay be formed from a dielectric material. Spacers 110 may serve thepurpose of separating the gate components from other components thatwill be formed proximate to the gate 102 during a later fabricationprocess, for example. One or more components such as source/drainregions (not shown) may be at least partially formed by doping andsubsequent annealing. Embodiments of semiconductor devices such astransistors may vary, and the above-described device is provided forillustrative purposes. Fabrication of a semiconductor device such aspartially formed transistor 100 is well known in the art, and may varyfrom the above-described method and still be in accordance with theclaimed subject matter.

The topography of device 100 varies across the device. For example, thetop surface 116 of substrate 108 is in a lower relative verticalposition than the top surface 114 of gate 102. Because the topographydiffers among these top surfaces, methods of thermally treating devicessuch as device 100 may result in uneven heating among these surfaces.Just as topography differs among surfaces, topology may also differamong surfaces. Top surfaces 114 and 116 represent two surfaces havingdifferent topologies in respect of the surface materials and/orsub-surface materials used to form the structures embodying the topsurfaces. Because the topology, including heat conductioncharacteristics of the underlying layers, may differ among thesesurfaces, methods of thermally treating devices such as device 100 mayresult in uneven heating among these surfaces, as described previously.

During the formation of a semiconductor device, and prior to a heattreating process such as annealing, a layer 112 may be formed ordeposited on at least a portion of one or more top surfaces of a devicesuch as partially formed transistor 101 of FIG. 1 b. Layer 112 may becomprised of material that may have a higher melting point that one ormore materials comprising device 101, such as a metal, for example.During a subsequent heat treating process, one or more components of adevice that has a layer 112 formed or deposited thereon may begin tosoften, but layer 112 may retain its shape and stiffness and may notsoften, depending on the particular material used to form layer 112.This may result, for example, in device 101 retaining its shape duringthermal treating. However, as will be shown in greater detail later,this will not serve to reduce the problems encountered due to thetendency of laser light to be pattern dependent, and the resultinguneven heating resulting from varying topographies of a device.Specifically, uneven heating of the device and the problems associatedwith uneven heating may still result from laser annealing, even with thelayer 112 formed on the device.

FIG. 2 a and FIG. 2 b illustrate utilization of one embodiment of acapping layer in accordance with the claimed subject matter. Shown inFIG. 2 a is partially fabricated transistor 200, which may bestructurally similar to partially formed transistor 100 of FIG. 1.Partially formed transistor 200 may be embodied on a silicon wafer (notshown). Partially formed transistor 200 may include a substrate 208,which may comprise silicon, for example. A gate dielectric 206 istypically formed on the substrate, and may comprise silicon dioxide orother dielectric material, for example. Gate 202 is typically formed onthe gate dielectric. Gate 202 is formed from an electrically conductivematerial, such as a metal or polysilicon based material, for example.Spacers 210 may be formed on the sides of the gate 202 and gatedielectric 206, and may be formed from a dielectric material. A portionof the substrate 208 may be implanted with dopant (not shown). One ormore heat treating processes may be utilized to activate the dopant.Formed on at least a portion of one or more surfaces of partially formedtransistor 200 is a first layer 218.

First layer 218 may be comprised of one or more materials, or acombination of materials. In an embodiment, first layer 218 may includesilicon dioxide (SiO₂). In another embodiment, first layer 218 mayinclude silicon nitride (Si₃N₄). In another embodiment, first layer 218may include a combination of silicon dioxide (SiO₂) and silicon nitride(Si₃N₄). It will, of course, be understood that the claimed subjectmatter is not limited in this respect, but may comprise any materialcapable of being deposited one or more surfaces of a device such aspartially formed transistor 200, that exhibits desirable properties,such as a particular reflectivity, heat conduction, heat capacity orreactivity, as just a few examples. Additionally, first layer 218 may beformed by any number of methods, including chemical vapor deposition(CVD), one or more sputter processes, growing, or any number of otherwell known methods that may be incorporated for forming a layer such asfirst layer 218 on a surface, for example.

In one embodiment, first layer 218 is formed on a substantial amount ofthe exposed surfaces of partially formed transistor 200. The materialcomprising the first layer is selected based on a number ofcharacteristics, which may include melting point, shape retention, orlight absorption properties, and the ability to maintain mechanical andstructural integrity during irradiation, for example. In thisembodiment, first layer may comprise a silicon dioxide layer depositedby use of chemical vapor deposition, wherein the layer is deposited on asubstantial portion of the exposed surfaces of partially formedtransistor 200 to a thickness in the approximate range of 0.001 micronto 0.1 micron, for example, and may be formed to a substantially uniformthickness, for example, although the claimed subject matter is not solimited. A second layer may be subsequently formed on the top surface222 of first layer 218, as described in more detail in reference to FIG.2 b.

Shown in FIG. 2 b is partially fabricated transistor 201, which may bestructurally similar to partially formed transistor 200 of FIG. 2 a, butwith a second layer 220 formed thereon. Partially formed transistor 201may be embodied on a silicon wafer (not shown). Partially formedtransistor 201 may include a substrate 208, which may comprise silicon,for example. A gate dielectric 206 is typically formed on the substrate,and may comprise silicon dioxide or other dielectric material, forexample. Gate 202 is typically formed on the gate dielectric. Gate 202is formed from an electrically conductive material, such as a metal orpolysilicon based material, for example. Spacers 210 may be formed onthe sides of the gate 202 and gate dielectric 206, and may be formedfrom a dielectric material. A portion of the substrate 208 may beimplanted with dopant (not shown). One or more heat treating processesmay be utilized to activate the dopant. Second layer 220 may be formedon at least a portion of the top surface 222 of first layer 218.

Second layer 220 may be comprised of one or more materials, or acombination of materials. In an embodiment, second layer 220 may includetungsten, titanium, tantalum, or one or more metal nitrides such astitanium nitride (TiN) or tantalum nitride (TaN), for example. It isimportant to note, however, that the claimed subject matter is notlimited in this respect, but may comprise any material capable of beingdeposited one or more surfaces of a device such as partially formedtransistor 201 that exhibits desirable properties, such as a particularreflectivity, heat conduction, heat capacity or reactivity, and theability to be planarized, as just a few example. Additionally, secondlayer 220 may be formed by any number of methods, including chemicalvapor deposition (CVD), one or more sputter processes, growing, or anynumber of other well known methods that may be incorporated for forminga layer such as first layer 220 on a surface.

In one embodiment, first layer 220 is formed on a substantial amount ofthe top surface 222 of first layer 218. The material comprising thefirst layer is selected based on a number of characteristics, which mayinclude melting point, shape retention, or light absorption properties,and the ability to maintain mechanical and structural integrity duringirradiation or planarization, for example. In this embodiment, secondlayer 220 may comprise a titanium layer deposited by use of chemicalvapor deposition, wherein the layer is deposited on a substantialportion of the top surface 222 of first layer 218, and is formed to athickness substantially greater than the thickness of first layer 218.For example, first layer may have an approximate thickness of 0.1micron, and second layer may be formed on the first layer to anapproximate thickness of 1 micron, although, of course, the claimedsubject matter is not so limited. When formed, the top surface 224 ofsecond layer 220 may be substantially planar, although the claimedsubject matter is not so limited. For example, one or more processes maybe performed on a substantial portion of the top surface 224 of secondlayer 220, resulting in top surface 224 being substantially planar.

In one embodiment, after forming second layer 220, one or more chemicalmechanical processes may be used to substantially planarize the topsurface 224 of second layer 220, such as mechanical polishing or a wetetch, for example. This may result in the top surface 224 of secondlayer 220 being substantially planar. In this particular embodiment,after undergoing one or more chemical mechanical processes such asmechanical polishing, surface 224 may be substantially planar, andpartially formed transistor 201 may undergo one or more thermal treatingprocesses such as laser annealing. As described previously, laser lightmay be pattern dependent, and variations in the topography of a surfacebeing annealed may cause differing portions of the surface to absorbmore heat than others, which may result in overheating or underheatingof particular areas. However, when a substantially planar surface, suchas the top surface 224 of second layer 220 undergoes a laser annealingprocess, there are no substantial variations in topography, and thedevice 201 may be capable of absorbing laser light substantially evenly.This may result in one or more portions of device 201 being subjected toeven heating in a thermal treating process, and as a result, manyundesirable characteristics of uneven heating described previously maybe abated.

In one embodiment, it may be desirable to remove a portion of one ormore layers formed on a device such as device 201 after one or moreannealing processes. Removal may be by any number of methods, but it isenvisioned that for the above-described first and second layers, asecond layer 220 may be substantially removed prior to any removal offirst layer 218. In one embodiment, second layer 220 may be comprised ofa metal nitride (e.g. titanium nitride). In this embodiment, removal maybe accomplished by incorporating a hydroxide- or sulfuric acid/oxidantbased chemistry that may etch at least a portion of second layer 220.However, it is important to note that removal is not limited to a wetetch process or to use of a hydroxide or a sulfuric acid/oxidant basedchemistry, but any removal process that results in the removal of asubstantial portion of the second layer 220 is in accordance with theclaimed subject matter.

Removal of a substantial portion of the first layer 218 may beaccomplished in a similar manner to that used in the removal of thesecond layer 220. For example, in one embodiment, first layer 218 may becomprised of silicon dioxide (SiO₂). In this embodiment, removal may beaccomplished by incorporating a hydroxide- or sulfuric acid/oxidantbased chemistry that may etch at least a portion of first layer 218.However, it is important to note that removal is not limited to a wetetch process or to use of a hydroxide or a sulfuric acid/oxidant basedchemistry, but any removal process that results in the removal of asubstantial portion of the first layer 218 is in accordance with theclaimed subject matter.

It can be appreciated that the embodiments may be applied to theformation of any semiconductor device wherein annealing may bedesirable. Certain features of the embodiments of the claimed subjectmatter have been illustrated as described herein, however, manymodifications, substitutions, changes and equivalents will now occur tothose skilled in the art. Additionally, while several functional blocksand relations between them have been described in detail, it iscontemplated by those of skill in the art that several of the operationsmay be performed without the use of the others, or additional functionsor relationships between functions may be established and still be inaccordance with the claimed subject matter. It is, therefore, to beunderstood that the appended claims are intended to cover all suchmodifications and changes as fall within the true spirit of theembodiments of the claimed subject matter.

1-22. (canceled)
 23. A semiconductor apparatus, comprising: a substrateof silicon having one or more dopant impurities implanted in at least aportion of the substrate; a gate dielectric layer formed on at least aportion of the substrate; a conductive gate formed on the gatedielectric layer; a capping layer formed on a substantial portion of theexposed surface of the apparatus, wherein the capping layer issubstantially at least partially comprised of metal.
 24. The apparatusof claim 23, wherein the apparatus comprises one or more integratedcircuits (IC).
 25. The apparatus of claim 23, wherein at least one ofsaid one or more layers comprises a metal layer.
 26. The apparatus ofclaim 23, wherein at least one of said one or more layers comprises asilicon based layer.
 27. The apparatus of claim 25, wherein the metallayer comprises a titanium based layer.
 28. The apparatus of claim 26,wherein said silicon based layer comprises silicon dioxide.
 29. Theapparatus of claim 23, wherein one or more layers comprises a siliconbased layer, and one or more layers comprises a metal layer, the methodfurther comprising depositing the silicon based layer on a substantialportion of the exposed surface of the device, and subsequentlydepositing the metal layer on a substantial portion of the top surfaceof the silicon based layer to a substantially greater thickness thanthat of the silicon based layer.
 30. The apparatus of claim 26, whereinthe silicon based layer is deposited by chemical vapor deposition, andthe second layer is deposited by a sputter process.
 31. The apparatus ofclaim 23, wherein the semiconductor device comprises a plurality ofpartially formed transistors.
 32. The apparatus of claim 23, whereinsaid removing comprises selective removing, wherein the selectiveremoving comprises an etch that removes a substantial portion of the oneor more layers, selective to the top surface of the semiconductordevice.
 33. The apparatus of claim 23, wherein selective removingcomprises removing one or more sacrificial layers by using one or morechemicals selected based on the chemicals ability to remove one or moresacrificial layers without substantial removal of other materials on thesemiconductor device.
 34. The apparatus of claim 23, wherein saidremoving comprises a wet-etch.
 35. The apparatus of claim 23, whereinsaid wet etch comprises a hydroxide based wet etch.
 36. The apparatus ofclaim 23, wherein said wet etch comprises a sulfuric acid/oxidant basedwet etch.
 37. The apparatus of claim 23, wherein one or more layerscomprises a silicon based layer, and one or more layers comprises ametal layer, the method further comprising removing a substantialportion of metal layer, and subsequently removing a substantial portionof the silicon based layer.